Analog-to-digital converter

ABSTRACT

The invention relates to signal processing circuits, analog-to-digital conversion circuits (A/D conversion circuit) and track and hold and sample and hold circuits. A circuit transfers charge from a first capacitor to a second one where the transfer is enhanced by means of a control signal which influences the value of at least one capacitor. This circuit can be used as an amplifier or a sample and hold circuit, and does not consume any standing current. This circuit can be advantageously combined with a novel capacitor arrangement which allows the generation of multiple residues and reference levels, and the carrying out of multiple operations in parallel. This can improve the overall performance of analog-to-digital converters, including multi-step converters as pipeline and successive approximation converters. The present invention provides amplification and sampling of signals without standing current, and generation of many reference levels and multiple residues in parallel. The present invention allows to eliminate the integrators in traditional analog-to-digital converters and therefore offers reduces power and enhances performance of analog-to-digital converters.

REFERENCE DATA

This application is a continuation of International Patent ApplicationPCT/EP2005/051850 (WO2005/107079) filed on Apr. 26, 2005, claimingpriority of European patent application EP04101803 of Apr. 28, 2004, thecontents whereof are hereby incorporated.

FIELD OF THE INVENTION

The invention relates to signal processing circuits, amplifiers,analog-to-digital conversion circuits (A/D conversion circuit) and trackand hold and sample and hold circuits.

DESCRIPTION OF RELATED ART

The performance improvement of digital electronics over the past 30 to40 years has caused electronic systems to be implemented in a primarilydigital way. This has significantly raised the interest inanalog-to-digital converters which need to translate data from theanalog to the digital domain for these digital systems. Often theseconverter circuits are the bottleneck in terms of speed, resolution andpower for the full system, and they have therefore been the object ofintensive research.

The fastest converter still remains the flash converter which for an Nbit conversion of an input signal IN comprises 2 ^(N)−1 comparators CO1. . . CO2 ^(N)−1. Each of these comparators CO1 . . . CO2 ^(N)−1 isassociated with a certain input signal level and determines whether theinput signal is above or below this level. Often these reference levelsare generated by a string of resistors R1 . . . R2 ^(N)−1 normally ofsubstantially equal resistance value, in between voltages VX and VY.This results in a series of 2_(N)−1 reference voltages between VX andVY, which corresponds for this example to the input range.

Flash converters have two disadvantages for large values of N: thenumber of comparators explodes resulting in large area and powerconsumption, and the decrease of the distance between neighboring levelsputs severe requirements on the comparators which need to be able toreact on smaller signals with an increased precision. To reduce theerror on the comparator level, or the comparator offset, the size of thecomponents in the comparator has to be increased, and this leads tolarger parasitic capacitances. Therefore this increases the power andarea consumption even more for large values of N.

Therefore several other converter architectures have been developedwhich reduce the number of comparators. Several of these architecturescarry out the conversion in multiple phases with increasing accuracy.Each conversion phase consists of the coarse conversion and thedetermination of the residue. This residue is the difference between ananalog representation—provided by a digital-to-analog converter—of theresult of the coarse conversion and the original signal on which thecoarse conversion was carried out. The first coarse conversion iscarried out on the input signal while the other coarse conversions arecarried out on the residue obtained during the previous coarseconversion. Several families within this type of converter exist: thesuccessive approximation converter uses the same components duringsubsequent phases, the pipelined converter makes use of a pipeline wherethe residues are transferred to the next stage in the pipeline.

Usually these converters need accurate amplifiers to generate andamplify the residue, which often are implemented as integrators, whichcontain one or more capacitors in the feedback loop. The precision isobtained by means of extremely high open loop gains. These integratorsor accurate amplifiers are usually dominant in the power consumption ofthese converters.

In addition, closed loop operation requires care to guarantee stability,and typically results in operating bandwidths well below the fundamentallimits of the technology.

It is therefore a first aim of the invention to provide a means togenerate the residue which allows the use of simple open loop amplifiersfor its amplification. It is a second aim of the invention to provide anopen loop amplification scheme which is particularly suited for thisapplication.

Often the input signal of a converter is sampled onto sample capacitorswhich store the input signal in the form of electrical charge. Thischarge is often read by means of an integrator, which as described aboveis a power consuming circuit. It is therefore a third aim of the presentinvention to provide a means to sample and read the signal chargewithout the use of an integrator.

BRIEF SUMMARY OF THE INVENTION

According to the invention, these aims are achieved by a circuit havingthe characteristics of the independent claims, advantageous embodimentsbeing furthermore given by the dependent claims.

The first aim, to provide a means to generate the residue, is achievedin particular by a circuit using a special capacitor arrangement wherethe residue is generated simultaneously on several circuit nodes. Thecircuit allows the introduction of well-determined offsets between saidcircuit nodes. These offsets can be used as reference for subsequentconversion phases if open loop amplifiers are used to amplify theresidue. As will be seen further, this circuit using a special capacitorarrangement is quite flexible and can be adapted to manyanalog-to-digital converter architectures.

The second aim, to provide an open loop amplification means which isparticularly suited for residue amplification, is achieved by a chargetransfer circuit which, in contrast to charge coupled devices (CCD's),can be implemented in standard CMOS without modifications in technology.As will be seen further, this open loop circuit consumes no static powerconsumption and is capable of providing very large gains. In additionthis amplification means is particularly suited to allow the sampling ofcharge and therefore provides the means to achieve the third aim of theinvention, to avoid the use of an integrator in the sample and holdcircuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention and its additional features, which may optionally be usedto implement the invention to best advantage, will be apparent from andelucidated with reference to the embodiments described hereafter withreference to the accompanying drawings, wherein:

FIG. 1 shows a prior art sampling and comparison circuit used as astarting point to explain the circuit according to the invention;

FIG. 2 illustrates a preferred embodiment of an analog-to-digitalconverter with a special capacitor arrangement according to theinvention;

FIG. 3 a illustrates a way to transfer charge from one capacitor toanother according to the invention;

FIG. 3 b shows the control signals for the circuit shown in FIG. 3 a;

FIG. 4 shows a preferred embodiment according to the present invention;

FIG. 5 a shows another preferred embodiment according to the presentinvention;

FIG. 5 b shows the control signals for the embodiment shown in FIG. 5 a;

FIG. 6 a shows an embodiment according to the invention of a buildingblock for an analog-to-digital converter;

FIG. 6 b shows a more schematic representation of the embodiment of FIG.6 a;

FIG. 7 shows a preferred embodiment of an analog-to-digital converterwith a special capacitor arrangement and charge transfer circuitaccording to the invention;

FIG. 8 a shows a preferred embodiment of a sample and hold circuitaccording to the invention;

FIG. 8 b shows the control signals of the embodiment in FIG. 6 a;

FIG. 8 c shows another embodiment of a sample and hold circuit accordingto the invention;

FIG. 8 d shows an embodiment of a charge transfer pipeline according tothe present invention;

FIG. 8 e shows the control signals of the embodiment in FIG. 8 d;

FIG. 9 a shows a preferred embodiment of a building block of ananalog-to-digital converter according to the invention;

FIG. 9 b shows a schematic representation of the embodiment of FIG. 9 a;

FIG. 10 a shows a preferred embodiment of how the embodiment of FIG. 9 acan be incorporated in a larger building block of analog-to-digitalconverter;

FIG. 10 b shows a more schematic representation of the embodiment ofFIG. 10 a.

FIG. 11 shows how part of the embodiment shown in FIG. 10 a and 10 b canbe used to construct an analog-to-digital converter according to theinvention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a prior art building block of a converter, which allowssampling of the input signal, the comparison of this input signal to areference level, and to add a well-defined signal to this input signal.The operation of this circuit is particularly instructive for theoperation of a preferred embodiment according to the invention and willtherefore be explained in some detail. The circuit shown in FIG. 1 is adifferential circuit receiving two input signals INL and INR of whichthe difference needs to be converted. The circuit comprises a comparatorC with first and second inputs IL and IR and digital output D, whichreflects which of the two comparator inputs IL or IR is higher inpotential than the other. Note that the comparator C can comprise apreamplifier circuit to allow the comparison decision to be made onsignals of large amplitude. The first comparator input IL corresponds tothe first input signal INL and the second comparator input IRcorresponds to the second input signal INR. The first and secondcomparator inputs IL and IR can be shorted together by means of a switchH. The first comparator input IL can be connected to a first referencepotential Vm by means of a switch RL. Similarly the second comparatorinput IR can be connected to the first reference potential Vm by meansof a switch RR. The first comparator input IL is further connected tothe first terminal of a first and a second capacitor CUL and CUR,respectively. The second terminal UL of the first capacitor CUL can beconnected to a second reference potential Vu, the third referencepotential Vd, or the first input signal INL by means of the switch SUL.Similarly, the second terminal DL of the second capacitor CDL can beconnected to the second reference potential Vu, the third referencepotential Vd, or the first input signal INL by means of the switch SDL.Similarly the second comparator input IR is further connected to thefirst terminal of a third and a fourth capacitor CUR and CDR,respectively. The second terminal UR of the third capacitor CUR can beconnected to the second reference voltage Vu, the third referencepotential Vd, or the second input signal INR by means of the switch SUR.The second terminal UL of the fourth capacitor CUR can be connected tothe second reference voltage Vu, the third reference potential Vd, orthe second input signal INR by means of the switch SDR. Note that inpractice the switches SUL, SDL, SUR, SDR will consist of severalswitches to implement the switching function previously described. It isalso common practice to choose the third reference voltage Vd equal tothe circuit ground as that avoids the generation of one referencevoltage.

The operation of the circuit shown in FIG. 1 will now be furtherdescribed.

In a first phase, the input signals INL and INR are being tracked. Thenodes UL and DL are connected to the first input signal INL by means ofthe switches SUL and SDL. The nodes UR and DR are connected to thesecond input signal INR by means of the switches SUR and SDR. Theswitches RL and RR are closed to connect the first and second comparatorinputs IL and IR to the first reference voltage Vm, respectively. Theswitch H can be closed to reduce the resistance between the twocomparator outputs IL and IR. The hold command is given by opening theswitches RL, RR and H thus disconnecting the comparator inputs IL and IRfrom each other and from the first reference voltage Vm. Subsequently,the second terminals UL, DL, UR and DR of capacitors CUL, CDL, CUR andCDR are disconnected from the input signals INL and INR, UL and UR areconnected to the second reference voltage Vu and DL and DR to the thirdreference voltage Vd, all this by means of the switches SUL, SDL, SURand SDR. If the capacitance values of the first and fourth capacitor CULand CDR equal x times Cval, where x is a value between 0 and 1, and thecapacitance values of the second and third capacitor CDL and CUR equal(1−x) times Cval, the sum of the capacitance values of the first andsecond capacitors C1L and C2L is equal to the sum of the capacitancevalues of the third and fourth capacitors C1R and C2R, and equal toCval. Neglecting parasitic charge injection, moving the second terminalsof the first and second capacitors C1L and C2L from the input signal INLto the second and third reference voltage Vu and Vd respectively,injects a charge QL into the first comparator input IL equal to:QL=Cval(Vu−INL)x+Cval(Vd−INL)(1−x)

Similarly a charge QR is injected into the second comparator input IRequal to:QR=Cval(Vu−INR)(1−x)+Cval(Vd−INR)x

The difference Qdif between the charge QL injected into the firstcomparator input IL and the charge QR injected into the secondcomparator input IR is a measure of the differential input signalapplied to the comparator C. This difference Qdif equals:Qdif=QL−QR=Cval(INR−INL)+Cval(Vu−Vd)(1−2x)

Note that when the hold command is given, the first and secondcomparator inputs IL and IR are isolated in dc (only capacitive couplingto the exterior, neglecting leakage). This means that no net charge canbe transferred to these nodes any more. Therefore the difference Qdifwill be accommodated by some voltage shift on these nodes in order tobalance Qdif.

Note also that if Qdif is positive, the first comparator input IL of thecircuit will be at a higher potential than the second comparator input.However, the circuit in FIG. 1 behaves such that that means that thedifference between the second input signal INR and the first inputsignal INL is larger than the reference level (Vu−Vd)(2x−1), so a firstinput signal INL at a larger potential will yield a lower potential ofthe first comparator input IL after the hold command is given and thecapacitors CUL, CDL, CUR and CDR have been disconnected from the inputsignals and connected instead to either the second or third referencepotentials Vu or Vd.

The digital output D of the comparator C will be an approximativerepresentation of the sign of Qdif with an error determined bycomparator offset and other differential parasitics. Further examiningthe expression for this difference Qdif yields that the sign of thisdifference Qdif corresponds to whether the differential input IND, whichis the difference between the second and first input signals INR andINL, is above or below a voltage level equal to (2x−1)(Vu−Vd). So, byvarying the parameter x the reference level for the comparison can bevaried from the difference between the second and third referencevoltages Vu and Vd to minus this difference. For instance for equalcapacitance values for the first through the fourth capacitors C2L, C2L,C1R and C2R, x equals 0.5, and the reference level will equal zero, soin that case the comparator output D will ideally reflect whether thedifference between the first and second input signal INL and INR ispositive or negative. So, if x is varied uniformly between 0 and 1 for aseries of circuits as shown in FIG. 1, a flash converter can beconstructed.

After evaluation of the comparison the circuit in FIG. 1 can alsoperform a digital-to-analog conversion function, useful for a multistepconverter. Here we assume that the second reference potential Vu ishigher than the third reference potential Vd. If the comparison yieldedthat the difference signal Qdif was positive, the second terminals ULand DL of both the first and second capacitor CUL and CDL are linked tothe third reference voltage Vd by means of the switches SUL and SDL. Thesecond terminals UR and DR of both the third and fourth capacitor CURand CUR are linked to the second reference voltage Vu by means of theswitches SUR and SDR. If Qdif was evaluated to be negative, UL and DLare linked to the second reference voltage Vu, and UR and DR are linkedto the third reference voltage Vd, by means of the switches SUL, SDL,SUR and SDR, respectively.

Also for this case the difference Qdif2 between the charge QL2 injectedinto the first comparator input IL and the charge QR2 injected into thesecond comparator input IR can be calculated (Note that the chargeinjected is calculated with respect to the situation at the instant thehold command was given):

If Qdif was evaluated positive:Qdif2=QL2−QR2=Cval(Vd−INL)−Cval(Vu−INR)OrQdif2=Cval(INR−INL)−Cval(Vu−Vd)

And if Qdif was evaluated negative:Qdif2=Cval(INR−INL)+Cval(Vu−Vd)

Note that the circuit shown in FIG. 1 is differential. To obtain asingle-ended rather than a differential circuit, it is possible toconnect one of the comparator inputs, for instance the second comparatorinput IR, to the first reference potential Vm and to use only theswitches related to the first input signal INL and to the firstcomparator input IL in a similar way as previously described.

FIG. 2 shows a preferred embodiment of a circuit with the specialcapacitor arrangement according to the present invention. The figureshows the circuit for 4 comparison circuits, the extension to adifferent number of circuits should be obvious to a person skilled inthe art. The circuit of FIG. 2 is very similar to the circuit of FIG. 1repeated four times. It consists of four comparators C1 . . . C4, withdigital outputs D1 . . . D4, and first and second comparator inputs IL1. . . IL4 and IR1 . . . IR4. Switches RL1, RR1 and H1 allow to connectthe first and second comparator inputs IL1 and IR1 of the firstcomparator C1 to the first reference voltage Vm. Similarly, switches RL2. . . RL4, RR2 . . . RR4, H2 . . . H4 provide the same function for thefirst and second inputs IL2 . . . IL4 and IR2 . . . IR4 of the othercomparators C2 . . . C4. Similar to a four-times repetition of thecircuit of FIG. 1, the input signal INR−INL is sampled, and a comparisonis carried out between the sampled input signal INR−INL and fourdifferent levels determined by capacitor ratios. The difference with asimple four-times repetition of the circuit in FIG. 1 lies in thecapacitor array CCC and in how the comparison result affects theswitching of the capacitor array. A four-times repetition of the circuitin FIG. 1 would allow the sampling of the input signal and itscomparison to four different levels if the ratio x is varied for the fordifferent circuits. For a four-times repetition of the circuit of FIG.1, the output of each comparator will affect the setting of thecapacitors at its own inputs only. The purpose of the capacitorarrangement according to the invention is that the each of thecomparator outputs D1 . . . D4 will affect the switching of capacitorslinked to inputs of more than one comparator. For this example, aftercomparison, the output of each of the comparators affects the switchingof a capacitor at an input of every comparator in the circuit. In thecircuit of FIG. 2, switches SUL1, SDL1, SUR1 and SDR1 are controlled bythe comparator output D1 of the first comparator C1. Similarly SUL2,SDL2, SUR2 and SDR2 are controlled by the comparator output D2 of thesecond comparator C2,etc . . . SUL1 allows to connect the node UL1 tothe first input INL, the second reference voltage Vu, or the thirdreference voltage Vd. SDL1 allows to connect the node DL1 to the firstinput INL, the second reference voltage Vu, or the third referencevoltage Vd, etc . . . During tracking the nodes UL1 . . . UL4 and DL1 .. . DL4 are connected to the first input signal, and the nodes UR1 . . .UR4 and DR1 . . . DR4 are connected to the second input signal. For thecomparison UL1 . . . UL4 and UR1 . . . UR4 are connected to the secondreference voltage Vu, and DL1 . . . DL4 and DR1 . . . DR4 are connectedto the third reference voltage Vd. After comparison the comparatoroutput D1 of the first comparator affects the switching of SUL1, SDL1,SUR1 and SDR1 and therefore affects the potential of the nodes UL1, DL1,UR1 and DR1. If D1 is positive UL1 and DL1 will be connected to thethird reference voltage Vd, and UR1 and DR1 to the second referencevoltage. The opposite will be done if D1 is positive after thecomparison. The other comparator outputs will control the nodes UL2 . .. UL4, DL2 . . . DL4, UR2 . . . UR4, DR2 . . . DR4 in a similar way. Thetable below gives an overview of how the capacitor array is connected,and the value of the capacitors relative to a unit capacitor Cval toobtain a comparison reference level of −¾(Vu−Vd),−¼(Vu−Vd),¼(Vu−Vd), and¾(Vu−Vd) for the comparators C1 . . . C4, respectively. The value chosenfor the capacitors will create the same DAC value for all for of thefour comparator circuits after comparison, and the DAC values are−(Vu−Vd),−½(Vu−Vd),0 , ½(Vu−Vd),(Vu−Vd): for instance if the comparatoroutputs D1 and D2 are positive and D3 and D4 are negative, the DAC valuewill be set to zero. In other words, the circuit generates the residueat the inputs of each of the four comparators. CDL11 DL1 IL1 ⅛ CUR11 UR1IR1 ⅛ CUL11 UL1 IL1 ⅛ CDR11 DR1 IR1 ⅛ CUL21 UL1 IL2 ¼ CDR21 DR1 IR2 ¼CUL31 UL1 IL3 ¼ CDR31 DR1 IR3 ¼ CUL41 UL1 IL4 ¼ CDR41 DR1 IR3 ¼ CDL12DL2 IL1 ¼ CUR12 UR2 IR1 ¼ CDL22 UL2 IL2 ⅛ CDR22 DR2 IR2 ⅛ CUL22 UL2 IL2⅛ CDR22 DR2 IR2 ⅛ CUL32 UL2 IL3 ¼ CDR32 DR2 IR3 ¼ CUL42 UL2 IL4 ¼ CDR42DR2 IR3 ¼ CDL13 DL3 IL1 ¼ CUR13 UR3 IR1 ¼ CDL23 DL3 IL2 ¼ CUR23 UR3 IR2¼ CDL33 DL3 IL3 ⅛ CUR33 UR3 IR3 ⅛ CUL33 UL3 IL3 ⅛ CDR33 DR3 IR3 ⅛ CUL43UL3 IL4 ¼ CDR43 DR3 IR4 ¼ CDL14 DL4 IL1 ¼ CUR14 UR4 IR1 ¼ CDL24 DL4 IL2¼ CUR24 UR4 IR2 ¼ CDL34 DL4 IL2 ¼ CUR34 UR4 IR3 ¼ CDL44 DL4 IL4 ⅛ CUR44UR4 IR4 ⅛ CUL44 UL4 IL4 ⅛ CDR44 DR4 IR4 ⅛

This illustrates that this circuit can generate the residue R many timesin a simple way and this due to the capacitor arrangement CCC. Thiscapacitor arrangement CCC is novel, because the outputs of thecomparators affect the inputs of the different comparators by means ofdifferent capacitors. This is novel and is therefore an object of theinvention. In this example the inputs of every comparator are affectedby every comparator output by means of a separate capacitor. In general,the novelty of the capacitor arrangement is characterized by the factthat at least one comparator output affects the inputs of at least twocomparators through a separate set of capacitors.

In practice some well-determined offset can be subtracted from theresidue R at each of the comparator inputs. This offset could bedifferent for each of the comparator inputs, to allow immediatecomparison of the residue and the newly subtracted offset. This wouldallow to immediately compare the residue again to this offset or couldbe used as reference after open-loop amplification. This can be done byadding two capacitors to each comparator input, of which the sum of thecapacitance values is constant but their ratio xd varies for thedifferent comparators, as for the capacitors CUL,CDL,CUR and CDR in FIG.1, for instance connecting the first terminal of capacitors DUL1 andDDL1 to the first comparator input IL1 of the first comparator C1, andthe first terminal of capacitors DUR1 and DDR1 to the second comparatorinput IR1 of the first comparator C1. During tracking and comparison thesecond terminal of DUL1 and DUR1 is connected to the second referencevoltage Vu, and the second terminal of DDL1 and DDR1 to the thirdreference voltage Vd. After comparison, the second terminal Of DUL1 andDUR1 is connected to the third reference voltage Vd and the secondterminal of DDL1 and DDR1 is connected to the second reference voltageVu. This will create an offset at the input of the first comparator D1determined by the ratio xd between the capacitance values of DUL1 andDDL1 which in this example is the same as the ratio between DDR1 andDUR1.

Another possibility would be to add an array of capacitors similar tothe one shown in FIG. 2 which would not be switched during the firstconversion and which would be switched after the first conversion tocreate an offset, similar to the previous example, but which in thiscase is added or subtracted from the residue for a subsequentcomparison. This way a multibit successive approximation converter canbe implemented.

At a certain point the comparator offset might become too large makingit desirable to combine or average the residues at the differentcomparator inputs to a smaller number, which would then be more precisedue to averaging. This could be done by connecting all first inputs IL1. . . IL4 to the first input of a differential integrator and all secondinputs IR1 . . . IR4 to the second inputs of a differential integrator.This integrator would measure and amplify the charge left on thecomparator inputs, which is the residue. However, as explained in theintroduction this would be a power consuming solution. One could useopen-loop amplifiers, for instance differential pairs Diff1 . . . Diff4,IL1 being connected to the first input of the first differential pairDiff1, IL2 to the first input of the second differential pair Diff2, etc. . . , and IR1 . . . IR4 connected to the second input of thedifferential pairs Diff1 . . . Diff2, respectively. These differentialpairs would output differential currents Id1 . . . Id4, which can easilybe combined by linking the corresponding outputs together. However, anopen-loop amplifier does not have a well defined gain, and thereforesome reference needs to be provided. If we apply a well-determinedoffset−Delta at the inputs of comparators D1 and D2 and awell-determined offset+Delta at the inputs of comparators D3 and D4, wecan use this as a reference for further conversion steps, if we combinethe differential currents Id1 and Id2, and the differential currents Id3and Id4.

In a more realistic example one would often have many more comparators.In a preferred embodiment the outputs (the differential currents) of thecomparators would be combined in two groups, where there is a welldetermined offset between the resulting global differential currentoutputs. If these current signals are converted to voltage (for instanceby injecting them into a resistor) and buffered, we obtain four signals(the current signals were differential, so had a positive and a negativecurrent output), respectively proportional to Delta/2+R/2,−Delta/2+R/2,Delta/2−R/2, and −Delta/2−R/2. If Delta is chosen sufficientlylarge to guarantee it be larger than R, one can use a second circuitsimilar to the one in FIG. 2 where the switches SUL1, SDL1, SUR1 andSDR1, etc . . . now only connect to the electrodes corresponding to thesecond and third reference voltages Vu and Vd. However, on the side ofthe switches SUL1 and SDL1, the second reference voltage Vu is replacedby the signal proportional to Delta/2+R/2, and the third referencevoltage Vd is replaced by the signal proportional to −Delta/2+R/2. Onthe side of the switches SUR1 and SDR1, the second reference voltage Vuis replaced by Delta/2−R/1 and the third reference voltage Vd by−Delta/2−R/2. If the comparators in this second circuit are reset whenUL1 . . . UL4 in this second circuit are connected to the signalproportional to Delta/2+R/2 and DL1 . . . DL4 in this second circuit tothe signal proportional to −Delta/2+R/2, UR1 . . . UR4 in this secondcircuit to the signal proportional to Delta/2−R/2 and DR1 . . . DR4 inthis second circuit to the signal proportional to −Delta/2−R/2, andafter reset switched from the Vu terminal to the Vd terminal and viceversa, one obtains signals on the comparators which compare the residueto a well determined reference level in the interval −Delta . . . Deltadetermined by the capacitor ratios. This illustrates how making use ofthis novel capacitor array two times in the same circuit can be usedadvantageously to carry both signal and reference information andproceed with further conversions. Afterwards one can again switch backor not determined by the comparison result, and generate a new residueat the inputs of the comparators in this circuit similar to the circuitof FIG. 2.

Differential pairs were just one possible example of an open loopcircuit. Many more possibilities exist.

A further aim of the invention is to provide a means of amplificationparticularly suited for this purpose. As will become clear below thisnew way of amplification also allows signal storage, and thereforeallows, once the signal stored, to take away the input. This liberatesthe first converter stage for a new conversion and allows theconstruction of a pipelined converter. In addition this circuit is alsocapable of sampling the input signal without the use of an integrator.

The invention is based on capacitive charge redistribution, illustratedin FIG. 3 a. The first terminal of a first capacitor C1 in FIG. 3 can beconnected to the first terminal of a second capacitor by means of afirst switch S1, while the second terminal of the two capacitors arealways connected. A second switch S2 can connect the first to the secondterminal of the second capacitor C2 and reset C2. It is assumed here forsimplicity that charge injection due to the switches can be neglected.The first switch S1 is in the open position, and the second switch S2 isin the open position after a reset of the second capacitor C2. The firstcapacitor C1 carries a charge q. If the switch S1 is closed to connectthe first terminals of the first and second capacitors C1 and C2 somefraction of the charge q will be transferred from the first capacitor C1to the second capacitor C2. The remaining charge q1 on the firstcapacitor C1 and the resulting charge q2 on the second capacitor equal:q1=q/(1+C2/C1) and q2=q/(1+C1/C2)

So, the larger the second capacitor C2 the more charge it will receive.If the capacitance value of the second capacitor can be influenced bymeans of a control signal x_1 which severely increases the capacitancevalue of the second capacitor C2, most of the charge q is transferred tothe second capacitor C2. If then after opening the switch S1 the valueof the second capacitor is severely reduced, the charge q2 transferredto the second capacitor cannot escape from the second capacitor and willcause a large voltage to be developed across the second capacitor, whichcan be significantly larger than the voltage induced by the originalcharge q on the first capacitor C1. So, amplification and storage can berealized by exploiting the non-linearity of a circuit in which acapacitance value varies controlled by a control signal.

Note that the kTC noise normally present when switching capacitors canbe severely reduced when resetting the capacitor C2 by performing thereset while controlling the value of the capacitance C2 to its lowvalue.

FIG. 4 shows an embodiment where the second capacitor C2 has beenreplaced by MOS transistor, in this case an NMOS transistor T1. In theembodiment shown source and drain of T1 are connected to each other andto the switches S1 and S2. Source and drain will receive the charge.When the transistor is in the off state, the capacitance of thesource-drain electrode is very small, in the on-state this electrode isconnected to the channel which sees the gate capacitance and the fullwell or substrate capacitance. So, a transistor is ideally suited as avariable capacitor. In this embodiment source and drain both exist andare connected together. It should be clear that a gate next to adiffusion (so only one of the two) would function equally well.

In another non illustrated embodiment, a PMOS transitor could be usedinstead of the NMOS transistor T1.

Another embodiment is shown in FIG. 5 a. The non-linear capacitorelement comprises two transistors, an NMOS transistor Tn and a PMOStransistor Tp, of which the sources and drains which are all connectedtogether form the node to which the charge is transferred. FIG. 5 bshows the control signals for the embodiment in FIG. 5 a: during resetand amplification the transistors are driven in the off-state, duringcharge transfer they are switched on, which requires to drive the gateof the PMOS transistor with a signal of opposite polarity than thesignal driving the gate of the NMOS transistor.

A very significant advantage provided by the invention—as illustrated bythe embodiments already discussed—is that no standing current is neededto provide amplification.

This method of amplifying the voltage developed by a charge signal on acapacitor can be quite generally applied: for instance in sensorapplications, in pipelines for charge transfer, in analog-to-digitalconverters, in sample and hold circuits.

This method of amplification can be advantageously used inanalog-to-digital converters. An embodiment of a building block similarto the circuit shown in FIG. 1 is shown in FIG. 6 a. A switch SXL isinserted between the first comparator input IL and the capacitors CDLand CUL and a switch SXR is inserted between the second comparator inputIR and the capacitors CDR and CUR. Non-linear controllable capacitorelements NL and NR are connected to the first and second comparatorinputs IL and IR, respectively. The operation of the circuit is similarto the operation of the circuit shown in FIG. 1. During tracking thecomparator inputs IL and IR are connected to each other and to areference voltage Vm. Switches SXL and SXR are closed. The non-linearcapacitors NL and NR are controlled to a low capacitance value. Afterthe hold command is given and the inputs INL and INR are disconnectedfrom the circuit using the switches SUL, SUR, SDL and SDR, thecapacitors are connected to the second and third reference voltageinstead to define the comparator level, and the non-linear capacitors NLand NR are driven to high capacitance value. This transfers most of thecharge on the capacitors CUL, CUR, CDL and CDR to the comparator inputsIL and IR, after which the switches SXL and SXR are opened. Thenon-linear capacitances NL and NR are driven to low capacitance valuerealizing amplification prior to comparison by the comparator C. For thedigital-to-analog conversion function of the circuit, the switches SXLand SXR are closed again, and the capacitors are connected to the secondand third reference voltage Vu and Vd in the same way as for the circuitin FIG. 1. This embodiment illustrates again how the invention can beadvantageously used to provide amplification without standing current.

FIG. 6 b shows a more schematic representation of the embodiment shownin FIG. 6 a: comparator C, switches SXL and SXR, and switches H, RL, andRR, and non-linear capacitors NL and NR are all incorporated in oneblock Q.

FIG. 7 shows an embodiment of an analog-to-digital converter based onseveral blocks Q1 . . . Q4 according to the invention identical to theblock Q shown in FIG. 6 a and 6 b, and furthermore based on the specialcapacitor arrangement CCC according to the invention. The operation ofthe embodiment is similar to the embodiment shown in FIG. 2, with thenon-linear capacitor elements in the blocks Q1 . . . Q4 providingamplification without standing current to facilitate the comparison.

FIG. 8 a shows an embodiment of a sample and hold circuit according tothe present invention. The input signal IN is applied to the firstterminal of a capacitor CS which can be reset using the switch SS. Theother terminal of the capacitor CS can be connected to the non-linearcapacitor formed by the PMOS and NMOS transistor Tp1 and Tn1 of whichthe gates are controlled by the control signals xsb and xs,respectively, and of which sources and drains are all connected togetherand form the charge receiving electrode. A switch SR1 allows to resetthis charge receiving electrode to be reset to a reference voltage Vr.

The circuit operates as follows: in a first phase the capacitor CS isreset by means of the switch SS, and therefore both terminals of thecapacitor CS are connected to the input, and the net charge on thecapacitor CS is zero. At the same time the switch SR1 resets the node towhich charge will be transferred, while the control signals xs and xsbcontrol the transistors Tn1 and Tp1 to be off. The switch SS1 is open.At a certain moment the switches SS and RS1 are opened and the switchSS1 is closed, and the control signals xs and xsb are switched to turnthe transistors on. The terminal of CS linked by means of the switch SS1to the transistors will be pulled to the same voltage as the sources anddrains of the transistors Tn1 and Tp1. FIG. 8 b illustrates the controlsignals for the embodiment of a sample and hold circuit shown in FIG. 8a. FIG. 8 c shows another embodiment of a sample and hold circuitaccording to the present invention where now a second non-linearcapacitor element is added to the embodiment of FIG. 8 a. This secondnon-linear capacitor element comprises an NMOS transistor Tn2 and a PMOStransistor Tp2, can be reset by means of a switch SR2 to referencevoltage Vr, and can be connected to the capacitor CS by means of theswitch SS2. Introducing more than one non-linear capacitor in this wayallows to distribute sampled charge over several different electrodesfor future use.

FIG. 8 d shows an embodiment of how a charge transfer pipeline can becreated according to the present invention. The embodiment comprises thesample and hold circuit of FIG. 8 a, where now another non-linearcapacitance element is added. This second non-linear capacitor elementcomprises an NMOS transistor Tn3 and a PMOS transistor Tp3, can be resetusing the switch SR3 to the reference voltage Vr, and can be connectedto the first non-linear element by means of the switch SS3. The controlsignals are illustrated in FIG. 8 e. The operation of the circuit is asfollows: first the input signal IN is sampled onto the first non-linearelement as explained previously. After the hold command is given byopening the switch SS1, and after the control signals xs and xsb areswitched to lower the capacitance of the first non-linear element, thesecond non-linear capacitive element is reset by closing the switch SR3.After opening the switch SR3 again, switch SS3 is closed and the controlsignals xs3 and xs3b are switched to turn on the transistors Tn3 andTp3. This increases the capacitance of the second non-linear element. Ifthis capacitance is sufficiently large, the charge originally stored onthe first non-linear capacitive element will redistribute and almost befully transferred to the second non-linear capacitive element accordingto the present invention. More non-linear capacitive elements can beadded to increase the number of stages in the charge transfer pipelinechain.

Similar to the embodiment shown in FIG. 8 c charge can be transferred ina pipeline to two or more non-linear capacitive elements in parallel.Charge can also be transferred in a pipeline from more than one elementin a previous stage to an element of the subsequent stage in thepipeline.

It has to be noted that charge transfer in a pipeline according to thepresent invention is based on charge redistribution governed bycapacitance ratios. This is different from charge transfer in a pipelineof charge coupled devices (ccd), where charge is transferred betweenpotential wells created by pulsing MOS capacitors into deep depletionmode using a multiphase clock.

Charge transfer according to the present invention depends oncapacitance ratios and is therefore in practice never complete. It cantherefore be useful to sample reference signals and transfer the sampledcharge in an identical or very similar manner as the input signal orinput signals to obtain properly scaled reference signals, in particularreference voltages.

To combine the amplification according to the invention prior tocomparison with the sample and hold circuit according to the inventionand the special capacitor arrangement according to the invention, firstconsider the embodiment P according to the invention in FIG. 9 a, whichis identical to the embodiment Q of FIG. 7 of the invention, except thatthe switches SXL and SXR have been removed. FIG. 9 b shows a schematicrepresentation of this embodiment P.

FIG. 10 a shows an embodiment of how such an embodiment P of FIG. 9 canbe used to construct a building block for an analog-to-digital convertersimilar to the building block of FIG. 1. The capacitors CUL, CUR, CDLand CDR can still be connected to the second and third referencevoltages Vu and Vd in a similar way, but now the switches SUL, SDL, SURand SDR can connect the capacitors CUL, CUR, CDL and CDR to an electrodeCC which can be reset will not connect the terminals of said capacitorsCUL, CUR, CDL and CDR to one of the inputs INL or INR, but to anelectrode CC instead which can be reset to a reference voltage Vr bymeans of the switch SV. The other terminal of the capacitors CUL and CDLis connected to the input IL of the circuit P, and the other terminal ofthe capacitors CUR and CDR is connected to the input IR of the circuitP. The inputs INL and INR are connected to the first terminal ofcapacitors CSL and CSR, respectively, which can be reset by means of theswitches SSL and SSR, respectively. Switches SYL and SYR can connect thesecond terminal of CSL and the second terminal of CSR to the inputs ILand IR of the circuit P. The circuit operates as follows: during a firstphase switches SSL and SSR are closed to reset the capacitors CSL andCSR, respectively. At the same time switches SUL, SDL, SUR and SDRconnect the capacitors CUL, CUR, CDL and CDR to the electrode CC whichis reset to the reference voltage Vr. The inputs IL and IR of thecircuit P are reset to the reference voltage Vm. After opening theswitches SSL, SSR, RL, RR, and H (RL, RR and H comprised in P wereresetting the inputs IL and IR), switches SYL and SYR are closed to linkthe capacitors CSL and CSR to the inputs IL and IR, respectively. At thesame time the non-linear capacitors NL and NR are steered to maximumcapacitance value and charge is transferred to the inputs IL and IR.Thereafter switches SYL and SYR are opened and the non-linearcapacitance elements are steered to minimum value again. At that timealso the capacitors CUL and CUR are connected to the second referencevoltage Vu and the capacitors CDL and CDR are connected to the thirdreference voltage Vd to define the comparison level. Thedigital-to-analog conversion function of the circuit is similar to thatof the circuit in FIG. 1. The embodiment of FIG. 10a is schematicallyrepresented in FIG. 10 b where a circuit PP has four terminals IL, IRand the two inputs. The circuit PP comprises capacitors CSL, CSR, theswitches SSL and SSR, the switches SYL and SYR, and the circuit P.

FIG. 11 shows an embodiment of how circuits PP1 . . . PP4 identical tothe circuit PP shown in FIG. 10 can be linked to the special capacitorarrangement CCC according to the invention. The blocks PP1 . . . PP4receive the inputs INL and INR on the corresponding inputs, and areconnected to the capacitor arrangement CCC by means of their inputs ILand IR. The electrodes receiving INL and INR in FIG. 2 are hereconnected to an electrode CC which can be reset by means of a switch VVRto a reference potential Vr. The operation is similar to that of thecircuit of FIG. 10 a, with the difference that the special capacitorarrangement CCC provides the residue after comparison and application ofthe digital-to-analog conversion at the inputs of every block PP1 . . .PP2. In conclusion, the present invention provides amplification withoutstanding current, sampling of an input signal based on a non-linearcapacitor of which the capacitance can be controlled by a controlsignal. The invention further provides multiple residue and levelgeneration by means of a special capacitor arrangement. The inventiontherefore allows to construct analog-to-digital converters in whichintegrators and power consuming amplifiers with standing current can beeliminated which represent most of the power consumption in theseconverters. The multiple residue and level generation allows to carryout several conversion operations in parallel, and therefore improvesthe performance of the converter. Therefore this invention improves bothpower consumption and performance for these converters. Theamplification without standing current can be generally applied andprovides significant power savings for the same gain and operation speedcompared to traditional amplifiers.

The present invention may be embodied in other specific forms withoutdeparting from its spirit or essential characteristics. The describedembodiments are to be considered in all respects as illustrative and notrestrictive.

1. A circuit which transfers charge from a first capacitor to a secondcapacitor, notably by charge redistribution, wherein the value of atleast one of said capacitors is controlled by means of a control signal,notably so as to enhance the transfer.
 2. The circuit of claim 1,further comprising a first switch for connecting one terminal of saidfirst capacitor to one terminal of said second capacitor.
 3. The circuitof claim 1, further comprising a first switch for connecting oneterminal of said first capacitor to one terminal of said secondcapacitor, a second switch for resetting said second capacitor, andmeans for opening said first switch after said transfer of charge andbefore application of said control signal.
 4. The circuit of claim 1,said capacitor being made of at least one MOS-transistor, said controlsignal being applied to the gate of said MOS transistor.
 5. The circuitof claim 4, said capacitor comprising an NMOS and a PMOS transistor ofwhich the sources and drains are all connected together.
 6. The circuitof claim 5 used as an amplification means.
 7. The circuit of claim 5,used as a sample and hold means.
 8. The circuit of claim 1, whereinredistribution of charges between capacitors is applied to input signalsas well as to reference signals used in said circuit.
 9. The circuit ofclaim 1, wherein charges are transferred from a first element to morethan one other element.
 10. The circuit of claim 1, where charges aretransferred from more than one element to another element.
 11. Thecircuit of claim 1, further comprising a capacitor arrangementcomprising at least two comparison circuits, a series of capacitors,each capacitor having one terminal connected to a switch controlled byat least one comparison circuit, wherein the inputs of at least twodifferent comparison circuits are affected by two different sets ofcapacitors connected to switches controlled by at least one commoncomparison circuit.
 12. A circuit which transfers charge from a firstcapacitor to a second capacitor, at least one capacitor being made of atleast one MOS-transistor, said circuit comprising: a first switch forconnecting one terminal of said first capacitor to one terminal of saidsecond capacitor, a second switch for resetting said second capacitor,means for applying a control signal for controlling the value of atleast one of said capacitors means for opening said first switch after atransfer of charge and before application of said control signal.
 13. Acharge transfer pipeline comprising a plurality of circuits according toclaim
 1. 14. An amplifier comprising a charge redistribution circuitwhich transfers charge from a first capacitor to a second capacitor,wherein the value of at least one of said capacitors is controlled bymeans of a control signal, so as to enhance the transfer.
 15. A sampleand hold means comprising a charge redistribution circuit whichtransfers charge from a first capacitor to a second capacitor, whereinthe value of at least one of said capacitors is controlled by means of acontrol signal, so as to enhance the transfer.
 16. A method fortransferring charges from a first capacitor to a second capacitor,comprising: connecting a first terminal of said first capacitor to afirst terminal of said second capacitor by means of a first switch,opening said first switch, varying the value of said second capacitor bymeans of a control signal.
 17. The method of claim 16, furthercomprising an initial step during which said second capacitor is reset.18. A capacitor arrangement comprising: at least two comparisoncircuits, a series of capacitors, each capacitor having one terminalconnected to a switch controlled by at least one comparison circuit,wherein the inputs of at least two different comparison circuits areaffected by two different sets of capacitors connected to switchescontrolled by at least one common comparison circuit.
 19. The capacitorarrangement of claim 18, where the inputs of all comparison circuits areaffected by different sets of capacitors connected to switchescontrolled by at least one common comparison circuit.
 20. The capacitorarrangement of claim 19 where the inputs of all comparison circuits areaffected by the outputs of all comparison circuits and by different setof capacitors.
 21. The capacitor arrangement of claim 20, furthercomprising means to provide a predefined offset at the inputs of atleast two comparators of the series.
 22. An analog-to-digital converterpart comprising a capacitor arrangement with: at least two comparisoncircuits, a series of capacitors, each capacitor having one terminalconnected to a switch controlled by at least one comparison circuit,wherein the inputs of at least two different comparison circuits areaffected by two different sets of capacitors connected to switchescontrolled by at least one common comparison circuit.